The present invention relates to a technique of manufacturing (e.g., soldering and mounting) a device (e.g., BGA type semiconductor package on a printed wiring substrate). In particular, it relates to a technique of moderating stresses caused by the difference of thermal expansion coefficient between a substrate (e.g., printed wiring substrate) and a electronic component (e.g., BAG type semiconductor package) thereby preventing damages to a interface between the substrate and the electronic component.
The number of pins in the electronic component (e.g., Large scale integrated circuit, BGA type semiconductor packages) is increasing. Further, for ensuring more number of pins, the pin pitch has become finer and size of the electronic component has been increased.
The electronic component is mounted on the substrate. Accordingly, if the thermal expansion coefficient of the electronic component is different from that of the substrate, thermal stress occurs at the interface due to the temperature change caused by operation of the electronic component. The stress becomes larger as the size of the electronic component becomes larger or the pin pitch becomes finer. Then, due to the thermal stress, failures such as cracks may sometimes occur at the interface between the substrate and the electronic component, and reliability of the interface is deteriorated.
For example, when a circuit board of the electronic component is made of alumina ceramic, the thermal expansion coefficient is about 7 ppm/K. On the other hand, the thermal expansion coefficient of the substrate is about 16 ppm/K. The difference is about 9 ppm/K. Accordingly, large thermal stress occurs at the interface between the substrate and the electronic component. Therefore, failures such as cracks are caused by the thermal stress.
In view of the above, the following related art has been disclosed to solve such problems.
FIG. 8 shows a cross sectional view of a BGA type semiconductor device disclosed in Japanese Patent Application Laid-open No. 2000-58706. Pad 105 are arranged each at a predetermined position of a chip 101. The surface of the chip 101 excluding the pad 105 is covered with a non-photosensitive polyimide film 107. A photosensitive polyimide 102B is formed at a predetermined pattern to a corresponding location of a solder ball 104. A non-photosensitive polyimide 102A is formed on the photosensitive polyimide 102B. And the photosensitive polyimide 102B is layered on the non-photosensitive polyimide 102A. The polyimide films are stacked alternately to form an insulating layer 102. The insulating layer 102 is coated with a metal wiring 103. A side 106 of the insulating layer 102 and the non-photosensitive polyimide film 107 are coated with the metal wiring 103. The metal wiring 103 is connected to the pad 105. Then, the solder ball 104 is attached on the metal wiring 103.
The BGA type semiconductor device disclosed in Japanese Patent Application Laid-open No. 2000-58706, has an elastic insulating layer 102 prepared by stacking the polyimide resin above the chip 101. Cracks caused by thermal stress can be prevented by the elasticity of the insulating layer 102. By preventing cracks, the life of solder is extended.
Japanese Patent Application Laid-open No. 2000-277923 describes a structure of mounting a BGA semiconductor package to a substrate. In the structure, the BGA pad has an insulating resin of low-elasticity. Japanese Patent Application Laid-open No. 2000-277923 discloses a technique of absorbing the thermal stress caused by the difference of thermal expansion coefficient between the substrate and the BGA semiconductor package.
FIG. 9 is a view showing a mounted structure of an electronic component described in Japanese Patent Application Laid-open hei No. 11-284029. FIG. 9 is a cross sectional view of mounting a BGA package 151 to a multilayer substrate 153 having electrodes 152. Electrodes 152 which is formed each at a predetermined arrangement are arranged on the multilayer substrate 153 having a number of stacked wiring layers 158. The BGA package 151 is made by bellow. First, a semiconductor chip is mounted on an interposer 154 having a circuit wiring 154a by using an adhesive. Second, the semiconductor chip is electrically connected with the circuit wiring 154a by using Au (gold) wire. Third, the semiconductor chip and the Au wires are sealed by a sealing resin 155. Holes are formed in an array to the interposer 154 placed on the surface of the BGA package 151 opposed to the multilayer substrate. By fixing a conductive ball using an Ag (silver) paste 156 coated in the hole as a conductive adhesive, bumps 157 are arranged in an array at the face of the BGA package 151. The conductive ball constituting the bump 157 comprises a resin ball 157a coated with tin plating 157b. The arrangement pattern of the electrodes 152 corresponds to the arrangement of the bumps 157. When the BGA package 151 is mounted on the multilayer substrate 153, the bump 157 and the electrode 152 are adhered and secured respectively using the Ag paste 159.
According to the related art disclosed in Japanese Patent Application Laid-open hei No. 11-284029, when an impact is applied from the outside to the BGA package 151 and the multilayer substrate 153, the resin ball 157a is elastically deformed. Therefore, the failure caused by the stress is prevented.
Further, Japanese Patent Application Laid-open hei No. 10-173006 describes a semiconductor device in which an electrode of a semiconductor chip and a conductor of a wiring substrate are flip-chip connected by using a conductive material on the side of the semiconductor chip, a conductive resin ball comprising a resin ball and a conductive layer covering the surface thereof, and a conductive material on the side of the wiring substrate. Thus, the thermal stress caused by the difference of the thermal expansion efficient between the semiconductor chip and the wiring substrate is moderated by the deformation of the resin ball at low elasticity to improve the reliability of a connecting section. A shape of the conductive connecting element for connecting the semiconductor chip and the wiring substrate is not restricted to the spherical shape but may also be an optional shape such as columnar shape, a prismatic shape or the like.